This invention relates to digital adder circuits.
Adder circuits are known which are capable of adding operands of radix other than a power of two e.g. decimal operands. For example, U.S. Pat. No. 4,172,288 describes a method of adding two binary decimal (BCD) operands by first adding the operands as if they were pure binary numbers to form an intermediate result, and then, if necessary, adding a correction value of six to the intermediate result to give the correct BCD result. The condition for adding the correction value is that the intermediate result is grgreater than or equal to ten. However, a problem with this is that a normal binary adder does not have any logic for detecting whether the sum is greater than or equal to ten. As a result, special logic must be provided to do this.
U.S. Pat. No. 3,958,112 describes an alternative arrangement in which the correction value of six is always added to one of the operands before the operands are added together and then, if necessary, the correction value is subtracted from the result. The condition for subtracting the correction value is that the result of the addition is less than sixteen, which is an easy condition to detect since it is simply the inverse of the normal binary adder overflow condition. However, the addition of the correction value before the addition of the operands introduces an extra stage which slows down the overall operation of the circuit.
One object of the present invention is to avoid this reduction of operating speed.